The present invention relates to a method of forming an isolation structure of a semiconductor device. More particularly, the present invention relates to a method of forming an isolation structure of a semiconductor device, in which it can lower a field leakage and prevent an increase in the chip size and degradation of device characteristics.
To apply a high operating voltage to a semiconductor memory device, a high voltage device with a high blocking characteristic needs to be constructed. The flash memory device performs program, read and erase operations. To execute the program and erase operations, a high voltage is applied to the control gate or the bulk. The flash memory device accordingly requires the use of a high voltage transistor.
The program, read and erase operations are performed a page at a time. To control the program, read and erase operations, a page buffer is used to manage a string of cells. The page buffer also uses a high voltage transistor.
If the leakage current occurs between the junctions of adjacent high voltage transistors, a memory cell to which a high voltage is applied from a high voltage transistor cannot effectively serve as a storage device.
Furthermore, during the erase operation, a high erase voltage is applied to the bulk of the memory cell in order to form a forward bias between the bulk and the junction. If a breakdown voltage of the junction itself is lower than an erase operating voltage, the erase operating voltage is lowered due to the leakage current, resulting in chip erase fail.
In the related art, to lower the leakage current, one method used is to increase the distance between the junctions of the high voltage transistors. Another method involves injecting field-stop ions into the isolation trench so that a reverse bias is formed with respect to voltage conditions applied to the junction.
The method of increasing the distance between the junctions may include extending a horizontal distance between the junctions by widening a width of the isolation structure formed between the junctions or extending a vertical distance between the junctions by increasing the depth of the isolation trench.
However, the memory cell size increases if the width of the isolation structure is increased. This makes it difficult to make the device smaller. If the isolation trench is deep, it is not a significant problem in the peripheral region with a large pattern size, but burial failure occurs when the trench is buried with the insulating film in the memory cell region with a small pattern size, causing failure in the operation of the memory cell.
FIG. 1 is a graph showing a relationship between the Erase/Write (E/W) cycling characteristic and the depth of an isolation trench.
As shown in FIG. 1, the E/W cycling characteristic is relatively stable in a low trench cell with a shallow isolation trench having shallow depth. In a high trench cell with a deep isolation trench, however, a program threshold voltage (P) and an erase threshold voltage (E) abruptly rise after 1K E/W cycling, generating a device failure. Such a phenomenon is believed to occur because the burial characteristic of an insulating material is degraded as the depth of the trench is increased.
As an alternative method for overcoming the problem, a method in which a depth of the trench in the peripheral region having a high voltage device formed therein is deep while keeping shallow the depth of the trench in the memory cell region has been proposed.
To form a deep trench in the peripheral region, a dry etch process employing plasma is used. The plasma process causes the segregation of boron (B) injected into the substrate, thereby generating problems such as channel leakage, punch through and hump (i.e., leakage between the source and the drain). This leads to degraded device characteristics.
FIG. 2A is a graph showing the relationship between the drain current (Id) and the gate voltage (Vg) on a bulk-voltage (Vbulk) basis when the isolation trench is deep. FIG. 2B is a graph showing the relationship between the drain current (Id) and the gate voltage (Vg) on a bulk-voltage (Vbulk) basis when the isolation trench is shallow.
From FIGS. 2A and 2B, it can be seen that a hump is not generated when the isolation trench is shallow. When the isolation trench is deep, however, the boron segregation in the active region results when a deep trench is formed. As the leakage occurs between the source and the drain, a hump in which a graph curve showing variation in the drain current (Id) depending on the gate voltage (Vg) is distorted is caused.
Furthermore, to form the trenches having different depths in the memory cell region and the peripheral region, three or more processes including a photolithography process, an etch process and a cleaning process are additionally performed. This increases the manufacturing cost and delays the device fabrication.
On the other hand, in the event that a field stop ion is injected below the isolation trench in order to form a reverse bias with respect to a voltage condition applied to the junction, if a breakdown voltage (BV) of the junction is lower than an erase voltage, the erase voltage is lowered due to the leakage and chip erase fail results.
FIG. 3 is a graph illustrating a phenomenon in which the erase rate decreases as a junction breakdown voltage of a high voltage transistor is lowered.
From FIG. 3, it can be seen that if the junction breakdown voltage (BV) is lowered, the erase time is increased if the cell threshold voltage is kept the same. In other words, the erase rate is lowered. Accordingly, since the erase is not completely performed, chip erase fail results.